The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Bluetooth devices provide connectivity for voice and data between wireless devices. FIG. 1A illustrates an example of a receiver 14 used in a Bluetooth device. The receiver 14 includes an antenna 20 that is connected to a front end module 24. The antenna 20 and the front end module 24 receive analog radio frequency (RF) signals. The analog RF signals output by the front end module 24 are input to a low noise amplifier 28, which amplifies the analog RF signals. A mixer 32 receives the analog RF signals output by the low noise amplifier 28 and an output of an oscillator 36. The mixer 32 converts the analog RF signals to baseband signals.
Further signal conditioning may be performed on the baseband signals. A filter 40 receives an output of the mixer 32. A first variable gain amplifier (VGA) 44 receives an output of the filter 40. A filter 46 receives an output of the VGA 44. A second VGA 48 receives an output of the filter 46. An analog to digital converter (ADC) 52 converts the filtered analog signal to a digital signal. A demodulation module 54 receives the digital signal from the ADC 52 and demodulates the digital signal to recover data bits. The demodulation module 54 may include a square-root-raised-cosine (SRRC) filter (not shown) that is matched to an SRRC filter in a Bluetooth transmitter (not shown).
When operating in a basic data rate (BDR) mode, a symbol rate of the digital signal output by the ADC 52 is 1 MHz with each symbol including one bit. When operating in enhanced data rate (EDR) modes, the symbol rate is 1 MHz, however each symbol represents two or three bits to provide 2 MHz or 3 MHz data rates, respectively.
FIG. 1B illustrates a BDR packet format, and FIG. 1C illustrates an EDR packet format. In FIG. 1B, the BDR packet begins with an access code and header. The access code is used for synchronization, DC-offset compensation, and identification of packets in a physical channel. Access codes are also used in paging, inquiry, and park operations in a Bluetooth system. The header includes link control information that includes packet type and link type. The link type determines the format of the payload that follows the access code and header. The payload may include user information and control information.
The user information may include data or voice or a combination of the two. The payload may also include control data used for device identity and provide real-time clock information. The payload may also include additional data for error discovery and recovery such as the cyclic redundancy check (CRC) and forward error correction (FEC) information.
The BDR packet in FIG. 1B is transmitted with Gaussian frequency shift keying (GFSK) modulation. The EDR packet in FIG. 1C changes from GFSK modulation to differential phase shift keying (DPSK) after the packet header. As a result, additional timing and control information is required for synchronizing to the new modulation format. The EDR packet uses the same access code and header definitions as the BDR packet, including the modulation format.
Following the header, the EDR packet includes a guard period that allows a receiver time to prepare for the change in modulation to DPSK. The guard time is followed by a synchronization sequence that includes a reference symbol and multiple DPSK symbols. This sequence is required for synchronizing the symbol timing and phase for one of the two modulation types used in the EDR packet. The payload in the EDR packet may include user information and control information based on the type of packet transmitted.
The EDR mode for the 2 Mb/s data rate uses differential-encoded quadrature phase shift keying (DQPSK). The DQPSK signal can be demodulated without estimating the carrier phase. Instead, the phase of a first symbol is compared to the phase of a second symbol. The amount of phase shift is used to estimate the received data.
The EDR mode for the 3 Mb/s data rate uses 8-ary differential encoded phase shift keying (8-DPSK). The further increase in the data rate is achieved through the addition of four more constellation points for each symbol. The total of eight constellation points allows a transmission rate of three bits per symbol. This type of modulation has many of the same benefits as DQPSK including non-coherent demodulation.
Referring back to FIG. 1A, the demodulation module 54 typically uses a Square Root Raised Cosine (SRRCC) filter (not shown) for pulse shaping at the transmitter. The SRRC filter (not shown) in the demodulation module 54 is matched to the SRRC filter used in the transmitter. The SRRC filter cancels intersymbol interference (ISI) at an optimum 1 MHz sampling phase. The demodulation module 54 typically identifies a sync word and performs differential detection. However, the performance or sensitivity of the differential detection approach used by the receiver is limited by incorrect sampling phase selection at power levels around sensitivity. Decision errors after a post slicer may also occur due to in-band noise.
FIG. 2 illustrates an EDR sync word detection module 100. An oversampling module 101 oversamples each symbol of an input signal T times and stores the oversampled signal in a FIFO buffer 102. For example T=8 in FIG. 2. A register 104 stores a predetermined EDR sync word. The EDR sync word detection module 100 includes a plurality of difference modules 108 and a plurality of multiplier modules 112. A first symbol of the predetermined EDR sync word is multiplied by a constant k in one of the multiplier modules 112-1. For example only, k=0.75, although other values may be used. An output of the multiplier module 112-1 is input to one of the difference modules 108-1. One of the samples (e.g., D0) of one of the symbols of the input signal is also input to the difference module 108-1. An output of the difference module 108-1 is input to a summing module 118.
Likewise, second and third symbols of the predetermined EDR sync word are multiplied by a constant k in the multiplier modules 112-2 and 112-3, respectively. Outputs of the multiplier module 112-2 and 112-3 are input to other ones of the difference modules 108-2 and 108-3, respectively. Other samples (e.g., D8 and D16) of other symbols of the input signal are also input to the difference modules 108-2 and 108-3, respectively. Outputs of the difference modules 108-2 and 108-3 are also input to the summing module 118. Additional symbols of the input signal are compared to other symbols of the predetermined EDR sync word.
The summing module 118 sums the differences generated by the difference modules 108 and outputs the sum to a comparing module 120. The comparing module 120 compares the sum to an EDR sync threshold and selectively generates an EDR sync found signal based on the comparison. For example, the comparing module 120 may generate the EDR sync found signal when the sum of the differences is less than the EDR sync threshold.
FIG. 3 illustrates a conventional differential detection module. Oversampled data symbols are received in FIFO buffer 150. A first symbol such as D0 is input to a first input of the multiplier 152. A second symbol such as D8 is input to a conjugate module 154, which provides a conjugate of the second symbol to a second input of the multiplier 152. An output of the multiplier 152 is output to a delay module 158, a coordinate rotation digital computer (cordic) module 162, a delay module 166 and a delay module 170. A frequency offset compensation module 174 receives an output of the delay module 170. An output of the frequency offset compensation module 174 is input to a slicer module 178, which outputs the data bits.